Adaptation of a fault–tolerant FPGA–based launch sequencer as a CubeSat payload processor

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Authors
Goff, Jordan K.
Subjects
Fault-tolerant
Payload Processor
Cube Satellite
Internal Triple Modular Redundancy
Field Programmable Gate Array
Universal Asynchronous Receiver Transmitter
Advisors
Loomis, Herchel H., Jr.
Newman, James H.
Date of Issue
2014-06
Date
Jun-14
Publisher
Monterey, California: Naval Postgraduate School
Language
Abstract
The purpose of this thesis is to design and test a fault–tolerant reduced instruction set computer processor running a subset of the multiprocessor without interlocked pipelined stages instruction set. This processor is implemented on a field programmable gate array (FPGA) and will be used as the foundation for a payload processor on a cube satellite developed at the Naval Postgraduate School. This thesis begins by considering the radiation effects present in the space environment and the various fault– tolerant designs used to guard against specific types of particle events. The internal triple modular redundancy method is selected and implemented at each pipeline stage of the processor. Next, a target FPGA is selected based on the performance requirements of the processor. The Virtex–5 (registered trademark of Xilinx, Inc.) is selected over the ProASIC3 (registered trademark of Microsemi, Inc.) due to its enhanced capabilities and potential to support expansion for future applications. The hardware design is presented as a hybrid Verilog and schematic based design. The system consists of the processor and a universal asynchronous receiver/transmitter that reads and writes data received from a generic serial interface. The device is simulated to ensure proper logic functionality. Conclusions and future work are discussed.
Type
Thesis
Description
Series/Report No
Department
Electrical and Computer Engineering
Organization
Identifiers
NPS Report Number
Sponsors
Funder
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Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
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