Programmable numerical function generators: Architectures and synthesis system
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Authors
Sasao, Tsutomu
Nagayama, Shinobu
Butler, Jon T.
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Date of Issue
2005-08
Date
Aug.24-26, 2005
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Abstract
This paper presents an architecture and a synthesis method for programmable numerical function generators of trigonometric functions, logarithm functions, square root, reciprocal, etc. Our architecture uses an LUT (Look-Up Table) cascade as the segment index encoder, compactly realizes various numerical functions, and is suitable for automatic synthesis. We have developed a synthesis system that converts MATLAB-like specification into HDL code. We propose and compare three architectures implemented as a FPGA (Field-Programmable Gate Array). Experimental results show the efficiency of our architecture and synthesis system.
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Article
Description
FPL2005, Tampere, Aug.24-26, 2005, pp.118-123.
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
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Department of Electrical and Computer Engineering
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Citation
T. Sasao, S. Nagayama, and J. T. Butler, “Programmable numerical function generators: Architectures and synthesis system," FPL2005 ,Tampere, Aug.24-26, 2005, pp.118-123.