Programmable Architectures and design methods for two-variable numeric function generators

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dc.contributor.authorNagayama, Shinobu
dc.contributor.authorSasao, Tsutomu
dc.contributor.authorButler, Jon T.
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.dateFebruary 2010
dc.date.accessioned2013-09-03T22:33:04Z
dc.date.available2013-09-03T22:33:04Z
dc.date.issued2010-02
dc.descriptionIPSJ Transactions on System LSI Design Methodology, Vol. 3, pp.118-129, Feb. 2010.en_US
dc.descriptionThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.description.abstractThis paper proposes programmable architectures and design methods for numeric function generators (NFGs) of two-variable functions. To realize a two-variable function in hardware, we partition a given domain of the function into segments, and approximate the function by a polynomial in each segment. This paper introduces two planar segmentation algorithms that efficiently partition a domain of a two-variable function...en_US
dc.identifier.citationS. Nagayama, T. Sasao and J. T. Butler, "Programmable Architectures and design methods for two-variable numeric function generators," IPSJ Transactions on System LSI Design Methodology, Vol. 3, pp.118-129, Feb. 2010.
dc.identifier.urihttps://hdl.handle.net/10945/35855
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.en_US
dc.titleProgrammable Architectures and design methods for two-variable numeric function generatorsen_US
dc.type.interactionArticleen_US
dspace.entity.typePublication
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