An investigation of memory latency reduction using an address prediction buffer
Loading...
Authors
Billingsley, Arthur Brooks, Jr.
Subjects
Memory latency
Computer architecture
Cache memory
Computer performance
Latency reduction
Cache hierarchy
Computer architecture
Cache memory
Computer performance
Latency reduction
Cache hierarchy
Advisors
Fouts, Douglas
Date of Issue
1992-12
Date
December 1992
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
Developing memory systems to support high speed processes is a major challenge to computers architects. Cache memories can improve system performance but the latency of main memory remains a major penalty for a cache-miss. A novel approach to improve systems performance is the use of a memory prediction buffer. The memory prediction buffer (MPB) is inserted between the cache and main memory. The MPB predicts the next cache-miss address and pre-fetches the data. The use of an MPB in a computer system is shown to decrease main memory latency and increase system performance.
Type
Thesis
Description
Series/Report No
Department
Department of Electrical and Computer Engineering
Organization
Naval Postgraduate School
Identifiers
NPS Report Number
Sponsors
Funder
Format
32 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.