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A quaternary decision diagram machine: Optimization of its code

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Authors
Sasao, Tsutomu
Nakahara, Hiroki
Matsuura, Munehiro
Kawamura, Yoshifumi
Butler, Jon T.
Subjects
quarternary decision diagram
branching program machine
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Date of Issue
2010-08
Date
August 2010
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Language
Abstract
This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed imrpovement of 1.28-2.02 times when QDDs are chosen. We consider 1- and 1-address BDD machines, and 3- and 4- address QDD machines, and we show a method to minimize the number of instructions.
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Article
Description
IEICE Transactions on Information and Systems, Vol. E93-D No. 8 pp. 2026-2035, Aug. 2010.
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
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Department of Electrical and Computer Engineering
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Citation
T. Sasao, H. Nakahara, K. Matsuura, Y. Kawamura, and J.T. Butler, "A quaternary decision diagram machine: Optimization of its code," IEICE Transactions on Information and Systems, Vol. E93-D No. 8 pp. 2026-2035, Aug. 2010.
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This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
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