Low-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes

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lowpowerhighspee00sheh.pdf (11.53 MB)
Authors
Shehata, Khaled Ali
Subjects
GaAs
Dynamic logic
CHIGFET
CGaAs
Two-phase dynamic FET logic
TPDL
Clock generator
Domino logic
N-P domino logic
CLA
Static logic
Advisors
Fouts, Douglas J.
Date of Issue
1996-09
Date
September 1996
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
The design and evaluation of several different low-power, high-speed, high-density complementary gallium arsenide (CGaAs) dynamic logic families that are compatible with existing CGaAs fabrication processes and design tools are documented. Circuits studied include Domino logic, N-P Domino logic and Two-Phase Dynamic FET Logic (TPDL). The TPDL circuits have been implemented and fabricated. The dynamic circuits are evaluated and compared with typical static logic circuits for speed, power consumption and layout area. Dynamic circuits are non-ratioed logic. Therefore, the transistor sizes can be minimized to reduce the layout area and the power dissipation of the circuits. Furthermore, dynamic circuits are faster than static circuits because they do not use PFETs for evaluation, only for precharging. Dynamic circuits consume less power than the static circuits because they have no short-circuit current and a reduced leakage current (only switching current flows in the dynamic circuits). This means that CGaAs dynamic logic circuits have higher speed than Directly-Coupled FET Logic (DCFL) and lower power consumption than complementary GaAs logic.
Type
Thesis
Description
URI
https://hdl.handle.net/10945/8639
Series/Report No
Department
Department of Electrical and Computer Engineering
Organization
Naval Postgraduate School
Identifiers
NPS Report Number
Sponsors
Funder
Format
258 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
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Copyright is reserved by the copyright owner
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