Design, construction and testing of a reduced-scale cascaded multi-level converter
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Authors
Crowe, Robert A.
Subjects
Advisors
Ashton, Robert W.
Ciezki, John G.
Date of Issue
2003-06
Date
Publisher
Monterey, California. Naval Postgraduate School
Language
Abstract
The main focus in the design of the next generation combatant, DD(X), is the US Navy's proposed Integrated Power System (IPS) which includes an all-electric propulsion drive system. The reduction of current waveform harmonics is critical in combatant propulsion systems such as the IPS. One method of reducing the current harmonics is to utilize a multilevel converter topology. The multi-level converter, as compared to a standard converter, features low dv/dt losses and low switching losses. This thesis examines the design, construction and testing of two multi-level converters operated in tandem, called a Cascaded Multi-Level Converter (CMLC). A digital logic switching circuit is designed and constructed to control the CMLC during the operational testing phase. The CMLC is demonstrated in a three-phase high-voltage configuration with 178.5 V zero-to-peak voltage, 2.10 A zero-to-peak current achieved using an R-L load.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
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NPS Report Number
Sponsors
Funder
Format
xvi, 127 p. : ill. (some col.) ;
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.