Design, construction and testing of a reduced-scale cascaded multi-level converter
| dc.contributor.advisor | Ashton, Robert W. | |
| dc.contributor.advisor | Ciezki, John G. | |
| dc.contributor.author | Crowe, Robert A. | |
| dc.contributor.department | Electrical Engineering | |
| dc.contributor.secondreader | Fouts, Douglas J. | |
| dc.date.accessioned | 2012-03-14T17:30:14Z | |
| dc.date.available | 2012-03-14T17:30:14Z | |
| dc.date.issued | 2003-06 | |
| dc.description.abstract | The main focus in the design of the next generation combatant, DD(X), is the US Navy's proposed Integrated Power System (IPS) which includes an all-electric propulsion drive system. The reduction of current waveform harmonics is critical in combatant propulsion systems such as the IPS. One method of reducing the current harmonics is to utilize a multilevel converter topology. The multi-level converter, as compared to a standard converter, features low dv/dt losses and low switching losses. This thesis examines the design, construction and testing of two multi-level converters operated in tandem, called a Cascaded Multi-Level Converter (CMLC). A digital logic switching circuit is designed and constructed to control the CMLC during the operational testing phase. The CMLC is demonstrated in a three-phase high-voltage configuration with 178.5 V zero-to-peak voltage, 2.10 A zero-to-peak current achieved using an R-L load. | en_US |
| dc.description.distributionstatement | Approved for public release; distribution is unlimited. | |
| dc.description.service | Lieutenant Commander, United States Navy | en_US |
| dc.description.uri | http://archive.org/details/designconstructi109451006 | |
| dc.format.extent | xvi, 127 p. : ill. (some col.) ; | en_US |
| dc.identifier.uri | https://hdl.handle.net/10945/1006 | |
| dc.publisher | Monterey, California. Naval Postgraduate School | en_US |
| dc.rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. | en_US |
| dc.subject.lcsh | Electric current converters | en_US |
| dc.subject.lcsh | Cascade converters | en_US |
| dc.title | Design, construction and testing of a reduced-scale cascaded multi-level converter | en_US |
| dc.type | Thesis | en_US |
| dspace.entity.type | Publication | |
| etd.thesisdegree.discipline | Electrical Engineering | en_US |
| etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
| etd.thesisdegree.level | Masters | en_US |
| etd.thesisdegree.name | M.S. in Electrical Engineering | en_US |
| etd.verified | no | en_US |
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