Simulation and analysis of Predictive Read Cache (PRC) performance
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Authors
Ҫamligüney, Altay
Subjects
Advisors
Fouts, Douglas J.
Date of Issue
1996-09
Date
September, 1996
Publisher
Language
en_US
Abstract
Memory subsystem bandwidth and latency are two major problems for modern computer architectures because memory speed should grow linearly with central processing unit (CPU) speed to maintain balanced system performance. However, in recent years, CPU speed has increased much more rapidly than memory speed. One common approach to memory system design, which can provide remarkable speedup, is to use one or more fast cache memories in a hierarchical architecture. The Predictive Read Cache is an alternative to second-level cache memories with its fast, simple and inexpensive design. Previous studies show that a small predictive read cache can give a better performance improvement than a much larger second-level cache for an Intel 486 microprocessor with a very small cost. This thesis continues previous efforts in design and optimization of the predictive read cache. Using address trace data from a SPARCstation 1+ miming Sun-OS and the SPEC benchmarks, the simulations demonstrate that a small predictive read cache can give even better performance improvements than the previous results obtained using 486 trace data. Since SPARC is the most common RISC architecture today, it was of great importance to simulate the PRC by using address traces captured from a SPARC-based platform. The predictive read cache is ideal for embedded systems in space based, weapons- based and portable computing applications that utilize advanced RISC processors.
Type
Thesis
Description
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NPS Report Number
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Format
xii, 43 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.