Multiple-valued programmable logic array minimization by concurrent multiple and mixed simulated annealing.
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Authors
Yildirim, Cem
Subjects
Multi-Valued Logic
Minimization Heuristics
PEA Design
Simulated Annealing
Minimization Heuristics
PEA Design
Simulated Annealing
Advisors
Butler, Jon T.
Date of Issue
1992-12
Date
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
The process of finding a guaranteed minimal solution for a multiple-valued
programmable logic expression requires an exhaustive search. Exhaustive search is
not very realistic because of enormous computation time required to reach a
solution. One of the heuristics to reduce this computation time and provide a nearminimal
solution is simulated annealing.
This thesis analyzes the use of loosely-coupled, course-grained parallel systems
for simulated annealing. This approach involves the use of multiple processors where
interprocess communication occurs only at the beginning and end of the process. In
this study, the relationship between the quality of solution, measured by the number
of products and computation time, and simulated annealing parameters are
investigated. A simulated annealing experiment is also investigated where two types
of moves are mixed. These approaches provide improvement in both the number of product terms and computation time.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
Naval Postgraduate School
Identifiers
NPS Report Number
Sponsors
Funder
Format
53 p.;28 cm.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.