Predictive Read Cache Memories for Reducing Primary Cache Miss Latency in Embedded Microprocessor Systems
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Authors
Fouts, Douglas Jai
Subjects
Advisors
Date of Issue
2000-04-04
Date
Publisher
The Government of the United States of America, as represented by the Secretary of the Navy, Washington, DC (US)
Language
Abstract
A predictive read cache reduces primary cache miss latency
in a microprocessor system that includes a microprocessor,
a main memory and a primary cache memory connected
between the main memory and the microprocessor via an
instruction address bus, a data address bus and a data bus.
The predictive read cache tracks the pattern of data read
addresses that cause misses in the primary cache and associates
the pattern with the specific instruction that generates
the pattern of miss addresses. When a pattern has been
determined, the address where the next cache data read miss
will occur is predicted and sent to memory at a time when
the memory is not busy with other transactions. The data at
the predicted miss address is then fetched and stored in the
predictive read cache. The next time a data read miss occurs
in the primary cache, if the miss address matches one of the
predicted miss addresses stored in the cache, then the
required data is immediately sent to the primary cache from
the predictive cache, rather than having to be read out of the
much slower main memory.
Type
Patent
Description
Patent
Series/Report No
Department
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
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Citation
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.