Analysis and design of CMOS voltage-folding circuits and their use in high speed ADCS
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Authors
Hart, Troy L.
Subjects
Advisors
Pace, Phillip
Date of Issue
1996-06
Date
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
This thesis provides a complete numerical analysis of a complementary metal oxide semiconductor (CMOS) analog folding circuit architecture, which is comprised of a number of parallel folding stages connected to an output stage. The bias point (reference voltage at which input signal is to be folded) and differential input responses are determined analytically. Current source requirements are also determined to ensure that the transistors remain in saturation. Using the analysis, a design process for implementing the folding circuit as a preprocessor for an analog to digital converter (ADC) is developed. A folding circuit preprocessor for a 6-bit optimum symmetrical number system (SNS) ADC is designed using this process. The designed circuit output is numerically analyzed and compared with HSPICE simulation results to verify the design process. Transfer function results are evaluated numerically to examine the preprocessor performance. Decimation bands are utilized within the ADC to eliminate coding errors. The effects of fabrication process tolerances, which alter the metal oxide semiconductor field effect transistor (MOSFET) parameters used in the analysis and design of the circuit, are quantified using a four corner approach.
Type
Thesis
Description
Electrical Engineering
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NPS Report Number
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Funder
Format
77 p.
Citation
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.