Implementation of the configurable fault tolerant system experiment on NPSAT-1

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dc.contributor.advisorLoomis, Herschel H., Jr.
dc.contributor.advisorNewman, James H.
dc.contributor.authorJackson, Andrew S.
dc.contributor.departmentElectrical and Computer Engineering
dc.contributor.departmentElectrical and Computer Engineeringen_US
dc.dateMar-16
dc.date.accessioned2016-04-29T21:19:31Z
dc.date.available2016-04-29T21:19:31Z
dc.date.issued2016-03
dc.description.abstractSpace is a harsh environment, full of high-energy radiation that can cause single-event effects (SEE) in orbiting satellites. Some of these effects, such as single-event upsets and single-event functional interrupts, occur when ionizing radiation causes the logical value in a memory element to change and are detectable and correctable through various error mitigation techniques. In this thesis, we develop and implement a hardware solution to combat these SEE for deployment as an experimental module on Naval Postgraduate School Satellite 1 (NPSAT-1). Based on the relatively benign orbit of NPSAT-1, industrial-grade, commercial-off-the-shelf components that have shown tolerance to radiation were selected to keep costs low. The primary source of mitigation relies on a globally triple-modular redundant microprocessor system instantiated inside of a XILINX Kintex-7 field-programmable gate array. The system consists of an open-source microprocessor without interlocked pipeline stages (MIPS) based processor softcore, a cached memory structure capable of accessing double-data rate type three and secure digital card memories, an interface to the main satellite bus, and XILINX’s soft error mitigation softcore. The hardware was tested both in and out of the system and verified to work on the ground with faults injected. Other techniques to mitigate errors due to SEE, such as memory scrubbing, are intended to be added before launch.en_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.
dc.description.serviceLieutenant, United States Navyen_US
dc.description.urihttp://archive.org/details/implementationof1094548536
dc.identifier.urihttps://hdl.handle.net/10945/48536
dc.publisherMonterey, California: Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.en_US
dc.subject.authorConfigurable Fault Tolerant Processor (CFTP)en_US
dc.subject.authorGlobal Triple-Modular Redundancy (GTMR)en_US
dc.subject.authorNPSAT-1en_US
dc.subject.authorField-Programmable Gate Array (FPGA)en_US
dc.subject.authorSingle Event Effect (SEE)en_US
dc.subject.authorcacheen_US
dc.subject.authormemory controlleren_US
dc.subject.authorerror mitigationen_US
dc.subject.authorhardware designen_US
dc.subject.authorsoftcore designen_US
dc.titleImplementation of the configurable fault tolerant system experiment on NPSAT-1en_US
dc.typeThesisen_US
dspace.entity.typePublication
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.nameMaster of Science in Electrical Engineeringen_US
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