The design of current-mode CMOS multiple-valued circuits
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Authors
Chang, Young-hoon
Butler, Jon T.
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Date of Issue
1991-05
Date
May 1991
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Abstract
We propose an algorithm for the design of multiple-valued current-mode CMOS logic (CMCL) circuits that is based on the cost-fable technique. The algorithm is a heuristic search technique AO' algorithm) 1O,ll] applied to an AND_OR tree. it is significantly faster than
Exhaustive Search while providing realizations that are almost as good. A new cost-table is also proposed that results in better realizations than obtained with a previous cost-table.
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Article
Description
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
Proceedings of the 21st International Symposium on Multiple-Valued Logic, May 1991, pp. 130-138
Proceedings of the 21st International Symposium on Multiple-Valued Logic, May 1991, pp. 130-138
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Department of Electrical and Computer Engineering
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Citation
The design of current-mode CMOS multiple-valued circuits," Proceedings of the 21st International Symposium on Multiple-Valued Logic, May 1991, pp. 130-138