A heat quench algorithm for the minimization of multiple-valued programmable logic arrays
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Authors
Dueck, Gerhard W.
Butler, Jon T.
Subjects
Multiple-valued logic
logic minimization
simulated annealing
heat quench
heuristic
sum-of-products
logic design
logic minimization
simulated annealing
heat quench
heuristic
sum-of-products
logic design
Advisors
Date of Issue
1996
Date
1996
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Abstract
imulated annealing has been used extensively to solve combinatorial problems. Although
it does not guarantee optimum results, results are often optimum or near optimum. The primary
disadvantage is slow speed. It has been suggested [1] that quenching (rapid cooling) yields results that are
far from optimum. We challenge this perception by showing a context in which quenching yields good
solutions with good computation speeds. In this paper, we present an algorithm in which quenching is
combined with rapid heating. We have successfully applied this algorithm to the multiple-valued logic
minimization problem. Our results suggest that this algorithm holds promise for problems where moves
exist that leave the cost of the current solution unchanged.
Key words: Multiple-valued logic, logic minimization, simulated annealing, heat quench, heuristic,
Type
Article
Description
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
Computer and Electrical Engineering Journal, Vol. 22, No. 2, 1996, pp. 103-107, 1996
Computer and Electrical Engineering Journal, Vol. 22, No. 2, 1996, pp. 103-107, 1996
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Department
Department of Electrical and Computer Engineering
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Citation
A heat-quench algorithm for the minimization of multiple-valued programmable logic arrays", Computer and Electrical Engineering Journal, Vol. 22, No. 2, 1996, pp. 103-107 1995