Design of multiple-valued programmable logic arrays
| dc.contributor.advisor | Butler, Jon T. | |
| dc.contributor.author | Ko, Yong Ha | |
| dc.contributor.corporate | Naval Postgraduate School (U.S.) | |
| dc.contributor.department | Electrical and Computer Engineering | |
| dc.contributor.secondreader | Yang, Chyan | |
| dc.date | December 1988 | |
| dc.date.accessioned | 2012-11-27T18:17:08Z | |
| dc.date.available | 2012-11-27T18:17:08Z | |
| dc.date.issued | 1988-12 | |
| dc.description.abstract | The goal of this thesis is the development of a programmable logic array (PLA) that accepts multiple-valued inputs and produces multiple valued outputs. The PLA is implemented in CMOS and multiple levels are encoded as current. It is programmed by choosing transistor geometries which control the current level at which the PLA reacts to inputs. An example of a 4-valued PLA is shown. As part of this research, a C program was written that produces a PLA layout. | |
| dc.description.distributionstatement | Approved for public release; distribution is unlimited. | |
| dc.description.service | Major, Republic of Korea Air Force | |
| dc.description.uri | http://archive.org/details/designofmultiple1094523167 | |
| dc.format.extent | 61 p. | en_US |
| dc.identifier.uri | https://hdl.handle.net/10945/23167 | |
| dc.language.iso | en_US | |
| dc.rights | Copyright is reserved by the copyright owner | |
| dc.subject.author | Multiple-valued logic function | en_US |
| dc.subject.author | Programmable logic array | en_US |
| dc.subject.author | Circuit generation | en_US |
| dc.subject.author | Simulation | en_US |
| dc.title | Design of multiple-valued programmable logic arrays | en_US |
| dc.type | Thesis | en_US |
| dspace.entity.type | Publication | |
| etd.thesisdegree.discipline | Electrical Engineering | en_US |
| etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
| etd.thesisdegree.level | Masters | en_US |
| etd.thesisdegree.name | M.S. in Electrical Engineering | en_US |
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