Recognition of VLSI module isomorphism
Loading...
Authors
Zagourakis, Emmanouil N.
Subjects
VLSI circuit verification
gate recognition
isomorphism identification
gate recognition
isomorphism identification
Advisors
Yang, Chyan
Date of Issue
1990-03
Date
March 1990
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
The purpose of this study is to determine whether or not a program could be developed to examine isomorphism between parts of a VLSI layout. Many simulation files, obtained through Magic's hierarchical extractor, were analyzed in order to develop a C program to accomplish recognition in several types of gates. This recognition gives signatures in order to check for isomorphism. The development and design of the algorithms used in different parts of the program are described. Results demonstrate that recognition of elements in a CMOS circuit is possible, even with moderate complexity structures. An appendix with the C program listings is included.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
vii, 142 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Approved for public release; distribution is unlimited.
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.