An extension to the multilevel logic simulator for microcomputers
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Authors
de Albuquerque, Julio Cesar Lopes
Subjects
Interative Compiler
MULTISIM Package
Multilevel simulator
MULTISIM Package
Multilevel simulator
Advisors
Rigas, H.B.
Date of Issue
1987-06
Date
Publisher
Language
en_US
Abstract
One of the most time consuming parts of the design process is the debugging of
the project. This happens when simple modifications to a circuit require recompilation
of the whole circuit.
In the CAD tool currently available for digital systems design, compilation is a
bottle neck. The VOHL system has an extremely efficient simulator phase and a
reasonable but slower compilation phase.
This thesis investigates a mechanism for eliminating the need to recompile the
complete circuit when small changes are needed.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
Naval Postgraduate School
Identifiers
NPS Report Number
Sponsors
Funder
Format
255 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.