Computer performance prediction of a data flow architecture.
Loading...
Authors
Hogen, David John
Subjects
data flow
dataflow
computer performance evaluation
computer performance prediction
dataflow
computer performance evaluation
computer performance prediction
Advisors
Cox, L.A. Jr.
Date of Issue
1981-06
Date
June 1981
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
Supercomputers capable of performing extremely high
speed computation nave been proposed, which are based on an
architecture known as data flow. Application of a Petri
net-based methodology is used to evaluate the performance
attainable by such an architecture. The architecture
evaluated is MIT's cell block data flow architecture which
is being developed to execute the applicative programming
language VAL.
Results Show that for the data flow architecture to
achieve its goal of high speed computation, intelligent
multiprogramming schemes need to be developed. One such
scheme, based on the notion of a "concurrency vector", is
introduced.
Type
Thesis
Description
Series/Report No
Department
Computer Science
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.