Boolean minimization of large relay interlock and control systems
| dc.contributor.advisor | Rotleaupe, Charles H. | |
| dc.contributor.author | Cook, John H., III | |
| dc.contributor.corporate | Naval Postgraduate School (U.S.) | |
| dc.contributor.department | Department of Electrical Engineering | |
| dc.date | 1963 | |
| dc.date.accessioned | 2012-08-29T23:29:17Z | |
| dc.date.available | 2012-08-29T23:29:17Z | |
| dc.date.issued | 1963 | |
| dc.description.abstract | The perfection of the transistor and the subsequent birth of a vast digital technology has focused special attention on the methods and mathematics of Boolean algebra. The result of this attention has been the development of powerful methods of synthesis and minimization of logic circuits. This area continues to be the subject of extensive research. The purpose of this paper is to explore the applicability of Boolean minimization methods to the design of large relay interlock and control systems. The investigation of an existing and representative system from the Boolean standpoint was judged to be the best way to accomplish this purpose. Accordingly, the system selected was the Livermore variable-energy 90-inch cyclotron located at the Lawrence Radiation Laboratory, Livermore, California. The conclusion is that for this class of system a working knowledge of elementary Boolean algebra and an engineer's normal intuition would be sufficient to achieve minimal design. As a bonus result, the symbolic notation known as "gate notation" was found to be a valuable aid in the representation and understanding of the interlock and control logic of the cyclotron. | en_US |
| dc.description.distributionstatement | Approved for public release; distribution is unlimited. | |
| dc.description.service | Lieutenant, United States Navy | en_US |
| dc.description.uri | http://archive.org/details/booleminimizatio1094511734 | |
| dc.identifier.uri | https://hdl.handle.net/10945/11734 | |
| dc.language.iso | en_US | |
| dc.publisher | Monterey, California: U.S. Naval Postgraduate School | en_US |
| dc.rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. | en_US |
| dc.title | Boolean minimization of large relay interlock and control systems | en_US |
| dc.type | Thesis | en_US |
| dspace.entity.type | Publication | |
| etd.thesisdegree.discipline | Electrical Engineering | en_US |
| etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
| etd.thesisdegree.level | Masters | en_US |
| etd.thesisdegree.name | M.S. in Electrical Engineering | en_US |
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