SEU design consideration for MESFETs on LT GaAs
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Authors
Weatherford, T.R.
Radice, R.
Eskins, D.
Devers, J.
Fouts, D.J.
Marshall, P.W.
Marshall, C.J.
Dietrich, H.
Twigg, M.
Milano, R.
Subjects
Advisors
Date of Issue
1997-12-01
Date
Publisher
IEEE
Language
en_US
Abstract
Computer simulation results are reported on transistor design and single-event charge collection modeling of metal-semiconductor field effect transistors (MESFETs) fabricated in the Vitesse H-GaAsIII{reg_sign} process on Low Temperature grown (LT) GaAs epitaxial layers. Tradeoffs in Single Event Upset (SEU) immunity and transistor design are discussed. Effects due to active loads and diffusion barriers are examined.
Type
Article
Description
The article of record as published may be found at http://dx.doi.org/101109/23.659047
Series/Report No
Department
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
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Format
Citation
Journal Name: IEEE Transactions on Nuclear Science; Journal Volume: 44; Journal Issue: 6Pt1; Conference: 34. IEEE nuclear and space radiation effects conference, Snowmass, CO (United States), 21-25 Jul 1997; Other Information: PBD: Dec 1997
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.