Publication:
Radiation tolerant, high speed, low power gallium arsenide logic

Loading...
Thumbnail Image
Authors
Wolfe, Kurt A.
Subjects
Single event upset
Gallium arsenid logic
Advisors
Fouts, Douglas J.
Date of Issue
1993-12
Date
December 1993
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
Gallium Arsenide (GaAs) circuits are largely immune to slowly accumulated radiation doses and therefore do not need the shielding required by complementary metal oxide semiconductor (CMOS) devices. This attribute renders GaAs circuits particularly attractive for space craft and military applications. However, it has been shown that GaAs circuits with short gate length transistors are excessively susceptible to single event upsets (SEU) due to enhanced charge collection at the edges of the gate called 'edge effect'. This thesis studies the SEU problem in two parts. Extensive computer modeling and simulation of a charged particle passing through various transistors of a low power, two-phase dynamic MESFET logic (IDFL) test chip was conducted using HSPICE in the first part. In the second part, new GaAs logic topologies are developed, simulated, and layed out in integrated circuits which require less power than directly coupled MESFET logic (DCFL) and should be less susceptible to single event upsets than TDFL circuits.
Type
Thesis
Description
Series/Report No
Department
Department of Electrical and Computer Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
111 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
Collections