Radiation tolerant, high speed, low power gallium arsenide logic
| dc.contributor.advisor | Fouts, Douglas J. | |
| dc.contributor.author | Wolfe, Kurt A. | |
| dc.contributor.corporate | Naval Postgraduate School (U.S.) | |
| dc.contributor.department | Department of Electrical and Computer Engineering | |
| dc.contributor.secondreader | Loomis, Herschel | |
| dc.date | December 1993 | |
| dc.date.accessioned | 2014-03-26T23:23:08Z | |
| dc.date.available | 2014-03-26T23:23:08Z | |
| dc.date.issued | 1993-12 | |
| dc.description.abstract | Gallium Arsenide (GaAs) circuits are largely immune to slowly accumulated radiation doses and therefore do not need the shielding required by complementary metal oxide semiconductor (CMOS) devices. This attribute renders GaAs circuits particularly attractive for space craft and military applications. However, it has been shown that GaAs circuits with short gate length transistors are excessively susceptible to single event upsets (SEU) due to enhanced charge collection at the edges of the gate called 'edge effect'. This thesis studies the SEU problem in two parts. Extensive computer modeling and simulation of a charged particle passing through various transistors of a low power, two-phase dynamic MESFET logic (IDFL) test chip was conducted using HSPICE in the first part. In the second part, new GaAs logic topologies are developed, simulated, and layed out in integrated circuits which require less power than directly coupled MESFET logic (DCFL) and should be less susceptible to single event upsets than TDFL circuits. | en_US |
| dc.description.distributionstatement | Approved for public release; distribution is unlimited. | |
| dc.description.service | Lieutenant, United States Navy | en_US |
| dc.description.uri | http://archive.org/details/radiationtoleran1094539759 | |
| dc.format.extent | 111 p. | en_US |
| dc.identifier.uri | https://hdl.handle.net/10945/39759 | |
| dc.language.iso | en_US | |
| dc.publisher | Monterey, California. Naval Postgraduate School | en_US |
| dc.rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. | en_US |
| dc.subject.author | Single event upset | en_US |
| dc.subject.author | Gallium arsenid logic | en_US |
| dc.title | Radiation tolerant, high speed, low power gallium arsenide logic | en_US |
| dc.type | Thesis | en_US |
| dspace.entity.type | Publication | |
| etd.thesisdegree.discipline | Electrical Engineering | en_US |
| etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
| etd.thesisdegree.level | Masters | en_US |
| etd.thesisdegree.name | M.S. in Electrical Engineering | en_US |
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