A single-chip false target radar image generator forcountering wideband imaging radars

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Authors
Fouts, Douglas J.
Pace, Phillip E.
Karow, Christopher
Ekestorm, Stig R.T.
Subjects
Digital image synthesis
Digital signal processing
Electronic warfare
Inverse synthetic aperture radar
Radar countermeasures
Synthetic aperture radar
Wideband imaging radar
Advisors
Date of Issue
2003-06
Date
Publisher
IEEE
Language
Abstract
This paper describes the theory, design, implementation, simulation, and testing of an ASIC capable of generating false target radar images for countering wideband synthetic aperture and inverse synthetic aperture imaging radars. The 5.5 6.1 mm IC has 81632 transistors, 132 I/O pins, and consumes 0.132 W at 70 MHz from a 3.3-V supply. An introduction to the application and operation of the ASIC in an electronic attack system is also presented. The false target image is fully programmable and the chip is capable of generating images of both small and large targets, even up to the size of an aircraft carrier. This is the first reported use of all-digital technology to generate false target radar images of large targets.
Type
Article
Description
Series/Report No
Department
Electrical and Computer Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Naval Research Laboratory
Office of Naval Research
Funder
Format
9 p.
Citation
D.J. Fouts, P.E. Pace, C. Karow, S.R.T. Ekestorm, "A single-chip false target radar image generator for countering wideband imaging radars," IEEE Journal of Solid-state Circuits, v.17, no 6 (June 2000), pp. 751-759.
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
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