Design, implementation, and testing of a high performance summation adder for radar image synthesis
| dc.contributor.advisor | Fouts, Douglas | |
| dc.contributor.advisor | Pace, Phillip | |
| dc.contributor.author | Amundson, Craig A. | |
| dc.contributor.department | Operations Research | |
| dc.date.accessioned | 2012-03-14T17:33:25Z | |
| dc.date.available | 2012-03-14T17:33:25Z | |
| dc.date.issued | 2001-09 | |
| dc.description.abstract | This thesis documents the schematic design, simulation, and fabrication mask layout of a highspeed 16-bit summation adder to be integrated into the Digital Image Synthesizer (DIS) Application Specific Integrated Circuit (ASIC). The DIS is a single-chip false target radar image generator to be used in countering wide band imaging radars. The DIS will calculate the false target image in 512 range bins. Each range bit utilizes two identical 16-bit binary adders. The 16-Bit Adder must compute the sum of two 16-bit numbers, providing a 16-bit sum, carry output, and overflow detection bit. The stated goal is for this adder to perform all of these functions in one pipeline stage while being clocked at 600 MHz. The first part of the design process includes an extensive analysis to utilize the fewest gates in designing the simplest adder that can achieve the 600 MHz goal. SPICE net lists are extracted from these schematic designs and simulations conducted to verify logic functionality and propagation speed. Mask layout of the verified design is constructed using a CMOS 0.18 micron process utilizing deep submicron technology with six metal interconnect layers. The mask layout design is verified by ensuring all design rule checks (DRC) and layout versus schematic (LVS) checks are satisfied. In aAddition, conclusions and recommendations are provided to assist other DIS project members in using this adder and the aforementioned design process for additional components of the DIS ASIC. | en_US |
| dc.description.service | US Marine Corps (USMC) author | en_US |
| dc.description.uri | http://archive.org/details/designimplementa109451883 | |
| dc.format.extent | xx, 172 p. ; | en_US |
| dc.identifier.oclc | 265305 | |
| dc.identifier.uri | https://hdl.handle.net/10945/1883 | |
| dc.publisher | Monterey, California. Naval Postgraduate School | en_US |
| dc.rights | This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States. | en_US |
| dc.title | Design, implementation, and testing of a high performance summation adder for radar image synthesis | en_US |
| dc.type | Thesis | en_US |
| dspace.entity.type | Publication | |
| etd.thesisdegree.discipline | Operations Research | en_US |
| etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
| etd.thesisdegree.level | Masters | en_US |
| etd.thesisdegree.name | Master of Sciences | en_US |
| etd.thesisdegree.name | M.S. | en_US |
| etd.verified | no | en_US |
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