Parallelizing SHA-256, SHA-1 and MD5 and AES on the cell broadband engine
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Authors
Dinolt, George
Allen, Bruce
Canright, David
Garfinkel, Simson
Subjects
Advisors
Date of Issue
2010-10-25
Date
Publisher
Monterey, California. Naval Postgraduate School
Language
Abstract
The Cell BE Architecture connects a Power processor with several synergistic processing units via a high-speed bus, allowing parallel processing on a chip. Architectural features enabling high speed performance include SIMD, many wide registers, DMA provisions, and dual-issue instructions. We have developed extraordinarily high performance implementatioins of SHA-256, SHA-1 and MD5 for this architecture. We have also developed parallelized implementations of AES Encryption.
Type
Technical Report
Description
Series/Report No
Department
Computer Science
Identifiers
NPS Report Number
NPS-CS-10-011
Sponsors
Funder
Format
iv, 49 p.: ill.;28 cm.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.