A Multi-threading Architecture for Multilevel Secure Transaction Processing
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Authors
Irvine, Cynthia E.
Isa, Haruna R.
Shockley, William R.
Subjects
Advisors
Date of Issue
1999-05-00
Date
Publisher
IEEE
Language
Abstract
A TCB and security kernel architecture for supporting multi-threaded, queue-driven transaction processing applications in a multilevel secure environment is presented. Our design exploits hardware security features of the Intel 80x86 processor family. Intel's CPU architecture provides hardware with two distinct descriptor tables. We use one of these in the usual way for process isolation. For each process, the descriptor table holds the descriptors of "system-low" segments, such as code segments, used by every thread in a process. We use the second table to hold descriptors for segments known to individual threads within the process. This allocation, together with an appropriately designed scheduling policy, permits us to avoid the full cost of process creation when only switching between threads of different security classes in the same process. Where large numbers of transactions are encountered on transaction queues, this approach has benefits over traditional multilevel systems.
Type
Conference Paper
Description
Series/Report No
Department
Computer Science (CS)
Identifiers
NPS Report Number
Sponsors
Naval Postgraduate School Center for INFOSEC Studies and Research
Funder
Format
15 p.
Citation
Proceedings of the 1999 IEEE Symposium on Security and Privacy, Oakland, CA, pp. 166-179, May 1999
Distribution Statement
Approved for public release, distribution unlimited
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.