Multiple-valued programmable logic array minimization by simulated annealing
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Authors
Dueck, Gerhard W.
Earle, Robert C.
Tirumalai, Parthasarathy
Butler, Jon T.
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Date of Issue
1992-05
Date
May 1992
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Abstract
We propose a solution to the minimization problem
of multiple-valued programmable logic arrays (PLA)
that uses simulated annealing. The algorithm accepts a
sum-ofproducts expression, divides and recombines the
product terms. gradually progressing toward a minimal
solution. The input expression can be user-specijied or
one produced by another heuristic. Unlike recently studied minimization techniques
(which are classijied as direct-cover methodr). our tech-
nique manipulates product terms directly, breaking them
up and joining them in different ways while reducing
the total number of product terms. We show two
mechanisms for recombining product terms and com-
pare the results with presently known heuristics. A
benefit of simulated annealing is that improved solutions
can be achieved by increasing computation time.
Type
Article
Description
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.
Proceedings of the 22nd International Symposium on Multiple-Valued Logic, May 1992, pp. 66-74
Proceedings of the 22nd International Symposium on Multiple-Valued Logic, May 1992, pp. 66-74
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Department of Electrical and Computer Engineering
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Citation
Multiple-valued programmable logic array minimization by simulated annealing," Proceedings of the 22nd International Symposium on Multiple-Valued Logic, May 1992, pp. 66-74