Multiple-valued programmable logic array minimization by simulated annealing

dc.contributor.authorDueck, Gerhard W.
dc.contributor.authorEarle, Robert C.
dc.contributor.authorTirumalai, Parthasarathy
dc.contributor.authorButler, Jon T.
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.dateMay 1992
dc.date.accessioned2013-09-03T22:30:04Z
dc.date.available2013-09-03T22:30:04Z
dc.date.issued1992-05
dc.descriptionThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.descriptionProceedings of the 22nd International Symposium on Multiple-Valued Logic, May 1992, pp. 66-74en_US
dc.description.abstractWe propose a solution to the minimization problem of multiple-valued programmable logic arrays (PLA) that uses simulated annealing. The algorithm accepts a sum-ofproducts expression, divides and recombines the product terms. gradually progressing toward a minimal solution. The input expression can be user-specijied or one produced by another heuristic. Unlike recently studied minimization techniques (which are classijied as direct-cover methodr). our tech- nique manipulates product terms directly, breaking them up and joining them in different ways while reducing the total number of product terms. We show two mechanisms for recombining product terms and com- pare the results with presently known heuristics. A benefit of simulated annealing is that improved solutions can be achieved by increasing computation time.en_US
dc.identifier.citationMultiple-valued programmable logic array minimization by simulated annealing," Proceedings of the 22nd International Symposium on Multiple-Valued Logic, May 1992, pp. 66-74
dc.identifier.urihttps://hdl.handle.net/10945/35755
dc.titleMultiple-valued programmable logic array minimization by simulated annealingen_US
dc.typeArticleen_US
dspace.entity.typePublication
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