VHDL modeling and simulation of a digital image synthesizer for countering ISAR
Loading...
Authors
Kantemir, Ozkan
Subjects
Digital image synthesizer
DIS
VLSI
ASIC
CMOS
VHDL
Active HDLTM
Aldec
Tanner
DIS
VLSI
ASIC
CMOS
VHDL
Active HDLTM
Aldec
Tanner
Advisors
Fouts, Douglas J.
Pace, Phillip E.
Date of Issue
2003-06
Date
June 2003
Publisher
Monterey, California. Naval Postgraduate School
Language
Abstract
This thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDLTM. Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP s and a cascade of 16 RBP s were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP s together, representing the actual 512 RBP s. As a result of this research, the majority of the DIS was functionally tested and verified.
Type
Thesis
Description
Series/Report No
Department
Electrical and Computer Engineering
Organization
Identifiers
NPS Report Number
Sponsors
Funder
Format
xvi, 146 p. : ill. (some col.)
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
Copyright is reserved by the copyright owner