VHDL modeling and simulation of a digital image synthesizer for countering ISAR

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dc.contributor.advisorFouts, Douglas J.
dc.contributor.advisorPace, Phillip E.
dc.contributor.authorKantemir, Ozkan
dc.contributor.departmentElectrical and Computer Engineering
dc.dateJune 2003
dc.date.accessioned2012-03-14T17:30:06Z
dc.date.available2012-03-14T17:30:06Z
dc.date.issued2003-06
dc.description.abstractThis thesis discusses VHDL modeling and simulation of a full custom Application Specific Integrated Circuit (ASIC) for a Digital Image Synthesizer (DIS). The DIS synthesizes the characteristic echo signature of a pre-selected target. It is mainly used against Inverse Synthetic Aperture Radars as an electronic counter measure. The VHDL description of the DIS architecture was exported from Tanner S-Edit, modified, and simulated in Aldec Active HDLTM. Simulation results were compared with C++ and Matlab simulation results for verification. Main subcomponents, a single Range Bin Processor (RBP), a cascade of 4 RBP s and a cascade of 16 RBP s were tested and verified. The overhead control circuitry, including Self Test Circuitry and Phase Extractor, was tested separately. Finally overall DIS was tested and verified using the control circuitry and a cascade of 4 RBP s together, representing the actual 512 RBP s. As a result of this research, the majority of the DIS was functionally tested and verified.en_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.
dc.description.serviceFirst Lieutenant, Turkish Armyen_US
dc.description.urihttp://archive.org/details/vhdlmodelingndsi10945964
dc.format.extentxvi, 146 p. : ill. (some col.)en_US
dc.identifier.urihttps://hdl.handle.net/10945/964
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsCopyright is reserved by the copyright owneren_US
dc.subject.authorDigital image synthesizeren_US
dc.subject.authorDISen_US
dc.subject.authorVLSIen_US
dc.subject.authorASICen_US
dc.subject.authorCMOSen_US
dc.subject.authorVHDLen_US
dc.subject.authorActive HDLTMen_US
dc.subject.authorAldecen_US
dc.subject.authorTanneren_US
dc.subject.lcshImage processingen_US
dc.subject.lcshDigital techniquesen_US
dc.subject.lcshElectronic countermeasuresen_US
dc.subject.lcshVHDL (Computer hardware description language)en_US
dc.titleVHDL modeling and simulation of a digital image synthesizer for countering ISARen_US
dc.typeThesisen_US
dspace.entity.typePublication
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.verifiednoen_US
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