Low voltage operational amplifier using parasitic bipolar transistors in CMOS

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Authors
Chunda, Jaime P.
Subjects
Advisors
Michael, Sherif
Date of Issue
1995-06
Date
June 1995
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
In this research, a low voltage BiCMOS operational amplifier was built using parasitic bipolar transistors in bulk CMOS technology. Designed and analyzed using PSPICE circuit simulation software, the amplifier achieves a gain bandwidth product of 20.24 MHz with power supply voltages of +/- 2.5 V. The simulation proved that the BiCMOS amplifier will operate with power supplies as low as +/- 0.6 V. Using MAGIC VLSI software, a layout of the amplifier was made for eventual fabrication in the MOSIS 2.0 m CMOS process.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
Identifiers
NPS Report Number
Sponsors
Funder
NA
Format
87 p.
Citation
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
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