A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation
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Authors
Richstein, James K.
Subjects
VLSI (very large scsale integration) design
MAGIC
CMOS
Optics
Image processing
MAGIC
CMOS
Optics
Image processing
Advisors
Pieper, Ronald J.
Fouts, Douglas J.
Date of Issue
1993-12
Date
December 1993
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
Histogram generation, a standard image processing operation, is a record of the intensity distribution in the image. Histogram generation has straight forward implementations on digital computers using high level languages. A prototype of an optical-electronic histogram generator has been designed and tested for 1-D objects using wirewrapped MSI TTL components. The system has shown to be fairly modular in design. The aspects of the extension to two dimensions and the VLSI implementation of this design are discussed. In this paper, we report a VLSI design to be used in a two-dimensional real-time histogram generation scheme. The overall system design is such that the electronic signal obtained from the optically scanned two-dimensional semi- opaque image is processed and displayed within a period of one cycle of the scanning process. Specifically, in the VLSI implementation of the two- dimensional histogram generator, modifications were made to the original design. For the two-dimensional application, the output controller was analyzed as a finite state machine. The process used to describe the required timing signals and translate them to a VLSI finite state machine using Computer Aided Design Tools is discussed. In addition, the circuitry for sampling, binning, and display have been combined with the timing circuitry on one IC. In the original design, the pulse width of the electronically sampled photodetector is limited with an analog one-shot. The high sampling rates associated with the extension to two dimensions requires significant reduction in the original 1-D prototype's sample pulse width of approximately 75 ns.
Type
Thesis
Description
Series/Report No
Department
Department of Electrical and Computer Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
82 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.