Publication:
Implementation of a Multiple Low-Rate Sampler Detector with Dual ADC Card And FPGA using Verilog HDL

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Authors
Canisio, Barth, Jr.
Subjects
ow-rate sampling
Multiple Low-Rate Sampling
MLRS
Nyquist
matched filter
simulated target
fixed-point
hardware implementation
FPGA
ADC
Verilog
HDL
Advisors
Romero, Ric
Fouts, Douglas J.
Date of Issue
2020-09
Date
September 2020
Publisher
Monterey, California. Naval Postgraduate School
Language
Abstract
Multiple Low-Rate Sampling (MLRS) technique offers a method in which the detection of specific wideband signals can be achieved using an effective sampling rate lower than what is required by the Nyquist-Shannon theorem. This thesis presents a hardware implementation of a radar detector that utilizes a two-channel MLRS receiver. We apply the MLRS theory using commercial-off-the-shelf analog-to-digital converters and a field-programmable gate array (FPGA). MLRS is implemented using the Verilog hardware description language. Additionally, aiming to reduce the computational cost and the overall signal processing complexity, we propose a fixed-point composite detector based on a single threshold derived from the multiple spectral dominant parts of the signal. The composite detector is implemented in the FPGA and is evaluated using external analog signals obtained from EM-simulated target responses. Applying two matched filters yet using one modified threshold introduced by the composite detection approach, the MLRS detector significantly increases the probability of detection while compensating for the increased false alarm rate.
Type
Thesis
Description
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Department
Electrical and Computer Engineering (ECE)
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Distribution Statement
Approved for public release; distribution is unlimited.
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Copyright is reserved by the copyright owner.
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