Implementation of a Multiple Low-Rate Sampler Detector with Dual ADC Card And FPGA using Verilog HDL
| dc.contributor.advisor | Romero, Ric | |
| dc.contributor.advisor | Fouts, Douglas J. | |
| dc.contributor.author | Canisio, Barth, Jr. | |
| dc.contributor.department | Electrical and Computer Engineering (ECE) | en_US |
| dc.date | September 2020 | |
| dc.date.accessioned | 2022-01-10T20:00:20Z | |
| dc.date.available | 2022-01-10T20:00:20Z | |
| dc.date.issued | 2020-09 | |
| dc.description.abstract | Multiple Low-Rate Sampling (MLRS) technique offers a method in which the detection of specific wideband signals can be achieved using an effective sampling rate lower than what is required by the Nyquist-Shannon theorem. This thesis presents a hardware implementation of a radar detector that utilizes a two-channel MLRS receiver. We apply the MLRS theory using commercial-off-the-shelf analog-to-digital converters and a field-programmable gate array (FPGA). MLRS is implemented using the Verilog hardware description language. Additionally, aiming to reduce the computational cost and the overall signal processing complexity, we propose a fixed-point composite detector based on a single threshold derived from the multiple spectral dominant parts of the signal. The composite detector is implemented in the FPGA and is evaluated using external analog signals obtained from EM-simulated target responses. Applying two matched filters yet using one modified threshold introduced by the composite detection approach, the MLRS detector significantly increases the probability of detection while compensating for the increased false alarm rate. | en_US |
| dc.description.distributionstatement | Approved for public release; distribution is unlimited. | en_US |
| dc.description.service | Lieutenant, Brazilian Navy | en_US |
| dc.identifier.curriculumcode | 590 (Electronic Systems Engineering) | |
| dc.identifier.uri | https://hdl.handle.net/10945/68631 | |
| dc.publisher | Monterey, California. Naval Postgraduate School | en_US |
| dc.rights | Copyright is reserved by the copyright owner. | en_US |
| dc.subject.author | ow-rate sampling | en_US |
| dc.subject.author | Multiple Low-Rate Sampling | en_US |
| dc.subject.author | MLRS | en_US |
| dc.subject.author | Nyquist | en_US |
| dc.subject.author | matched filter | en_US |
| dc.subject.author | simulated target | en_US |
| dc.subject.author | fixed-point | en_US |
| dc.subject.author | hardware implementation | en_US |
| dc.subject.author | FPGA | en_US |
| dc.subject.author | ADC | en_US |
| dc.subject.author | Verilog | en_US |
| dc.subject.author | HDL | en_US |
| dc.title | Implementation of a Multiple Low-Rate Sampler Detector with Dual ADC Card And FPGA using Verilog HDL | en_US |
| dc.type | Thesis | en_US |
| dspace.entity.type | Publication | |
| etd.thesisdegree.discipline | Electrical Engineering | en_US |
| etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
| etd.thesisdegree.level | Masters | en_US |
| etd.thesisdegree.name | M.S. in Electrical Engineering | en_US |
