VLSI design of a very fast pipelined carry look ahead adder
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Authors
Conradi, Joseph Robert
Hauenstein, Bruce Robert
Subjects
CAD tools
VLSI design
16-bit pipelined adder
VLSI design
16-bit pipelined adder
Advisors
Kirk, Donald E.
Date of Issue
1983-09
Date
September 1983
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
This thesis is an introduction to the use of computer-aided design (CAD tools for the design of very large scale integrated circuits (VLSI). The techniques are described and a tutorial is given which illustrates their use in the computing environment at the Naval Postgraduate School. The CAD tools were applied to design a 16-bit fast pipelined adder.
Type
Thesis
Description
Series/Report No
Department
Department of Electrical Engineering
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funding
Format
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.