ASIC BENCHMARKING FOR PROPOSED LIGHTWEIGHT CRYPTOGRAPHY STANDARD XOODYAK
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Authors
Wakeland, Michael C.
Subjects
lightweight
encryption
lightweight encryption
benchmarking
NIST
security
throughput
cell area
AES
Xoodyak
hardware
ASIC
SystemVerilog
hardware description
encryption
lightweight encryption
benchmarking
NIST
security
throughput
cell area
AES
Xoodyak
hardware
ASIC
SystemVerilog
hardware description
Advisors
Bollmann, Chad A.
Henry, Gaylord
Date of Issue
2022-03
Date
Publisher
Monterey, CA; Naval Postgraduate School
Language
Abstract
The U.S. National Institute of Standards and Technology (NIST) has initiated a process to standardize a “lightweight” cryptographic algorithm. Lightweight algorithms are designed for use in gate and performance-limited devices. This report compares an Application Specific Integrated Circuit (ASIC) implementation of the NIST Advanced Encryption Standard-128 (AES-128) and a competition finalist, Xoodyak. Implementations were written in SystemVerilog. Testing was performed using Vivado field programmable gate array simulations. Twenty six instances of AES and Xoodyak were built. These builds were optimized for throughput, clock frequency, and cell area, respectively. Size and performance benchmarks were obtained from builds using an 5nm and 16nm ASIC technology. Results indicate Xoodyak is capable of higher throughput than AES-128 while using a lower cell area.
Type
Thesis
Description
Series/Report No
Department
Electrical and Computer Engineering (ECE)
Organization
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NPS Report Number
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Citation
Distribution Statement
Approved for public release. Distribution is unlimited.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.