Circuit recognition of VLSI layouts

Abstract

The design process of a very large scale integrated (VLSI) circuit is time consuming, with design verification and timing analysis being two of the most tedious stages. The development of a computer-aided design (CAD) tool that verifies circuit design and timing will reduce the design time. The primary contribution of this thesis is to provide an initial tool that will assist VLSI designers with the verification of a circuit's design. This tool is the first of several modular programs which will give the designer the capability to quickly and accurately verify a VLSI circuit's design and timing. The primary goal of this thesis is to develop an algorithm that will recognize different elements within the simulation file of a Complementary Metal Oxide Silicon (CMOS) circuit. Several simulation files were obtained using Magic which is a layout editing system developed at the University of California, Berkeley. These simulation files were analyzed and a C program was written that would accomplish circuit recognition. Results demonstrate that recognition of not only transistors, inverters, and passgates is possible, but also complex elements. A section is provided that describes possible uses for this algorithm.