A VLSI design of a radix-4 floating point FFT butterfly.
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Authors
Zimmer, Michael Lee
Subjects
Digital Arithmetic
FFT Butterfly Design
Cyclic Spectrum Analysis
Genesil Silicon Complier
FFT Butterfly Design
Cyclic Spectrum Analysis
Genesil Silicon Complier
Advisors
Loomis, Herschel H., Jr.
Date of Issue
1991-12
Date
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
Cyclic Spectrum Analysis is used to exploit the
cyclostationary properties of signals and systems.
Implementing such a system will require high speed arithmetic
processing. Investigations into high speed arithmetic and FFT
design are conducted. Integrated circuits of a 45 MHz
floating point multiplier, adder, and rate-1/4 radix-4 FFT
butterfly, implemented with a 20-bit word size, are presented
using the Genesil Silicon Compiler.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
Naval Postgraduate School
Identifiers
NPS Report Number
Sponsors
Funder
Format
111 p.;28 cm.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.