Implementation of a Configurable Fault Tolerant Processor (CFTP) using Internal Triple Modular Redundancy (TMR)

Abstract

The environment of space is challenging to digital equipment due to the interaction between electrical systems and the radiation of space. One such effect is the Single Event Upset (SEU), which occurs when radiation causes a logical bit value to change. These effects are magnified in reconfigurable digital systems that utilize Field Programmable Gate Arrays (FPGA) because both the configuration and the data are susceptible to SEUs. Several techniques have been developed in order to mitigate these effects. One such technique, called Triple Modular Redundancy (TMR), is an architecture where three identical systems perform the same operation in parallel. The three outputs are applied to a voter circuit which would eliminate an SEU caused error. This thesis develops a five-stage pipelined Reduced Instruction Set Computer (RISC) microprocessor. A TMR architecture is then instantiated on an FPGA based circuit board. Instead of voting the processor outputs, the voting function is distributed and votes the outputs of all the internal pipeline registers. Even in the event of an SEU caused error, correct data is applied to the next pipeline stage. Finally this thesis describes and analyzes test data from radiation testing of the TMR system.