The error performance analysis over cyclic redundancy check codes.
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Authors
Yoon, Hee Byung.
Subjects
Error Performance Analysis;
Cyclic Redundancy Check Codes
CRC Block Burst Error
Cyclic Redundancy Check Codes
CRC Block Burst Error
Advisors
Yang, Chyan
Date of Issue
1991-06
Date
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
The burst error is generated in digital communication networks by various unpredictable conditions, which occur at high error rates, for short durations, and can impact services. To completely describe a burst error one has to know the bit pattern. This is impossible in practice on working systems. Therefore, under the memoryless binary symmetric channel (MBSC) assumptions, the performance evaluation or estimation schemes for digital signal 1 (DS1) transmission systems carrying live traffic is an interesting and important problem. This study will present some analytical methods, leading to efficient detecting algorithms of burst error using cyclic redundancy check (CRC) code. The definition of burst error is introduced using three different models. Among the three burst error models, the mathematical model is used in this study. The probability density function, function(b) of burst error of length b is proposed. The performance of CRC-n codes is evaluated and analyzed using function(b) through the use of a computer simulation model within CRC block burst error. The simulation result shows that the mean block burst error tends to approach the pattern of the burst error which random bit errors generate
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Computer Engineering
Organization
Naval Postgraduate School
Identifiers
NPS Report Number
Sponsors
Funder
Format
66 p.;28 cm.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.