A single-transistor memory cell and sense amplifier for a gallium arsenide dynamic random access memory
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Authors
Vagts, Christopher Bryan
Subjects
RAM
DRAM
Gallium Arsenide DRAM
Charge Storage in DRAM Cells
DRAM
Gallium Arsenide DRAM
Charge Storage in DRAM Cells
Advisors
Fouts, Douglas J.
Date of Issue
1992-12
Date
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
This thesis presents the design and layout of a Gallium Arsenide (GaAs) Dynamic Random
Access Memory (DRAM) cell. Attempts have been made at producing GaAs DRAM
cells, but these have dealt with modifications to the fabrication process, are expensive, and
have met with little success. An eight-address by one-bit memory is designed, simulated,
and laid out for a standard GaAs digital fabrication process. Three different configurations
of RAM cells are considered: the Three-Transistor RAM Cell, the One-Transistor RAM
Cell with a Diode and the One-Transistor RAM Cell with a capacitor. All are tested and
compared using the circuit simulator HSPICE. The chosen DRAM design uses the One-
Transistor RAM Cell with a parallel plate capacitor and a five-transistor differential sense
amplifier that handles reading as well as refresh of the memory cells. The differential sense
amplifier compares a dummy cell with a memory cell to perform a read. The required timing
is presented and demonstrated with read, write, and refresh cycles. Actions to minimize charge leakage are also considered and discussed. The design is simulated for access rates
of approximately five nanoseconds, but the basic design can work at much faster rates with
little modification.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Organization
Naval Postgraduate School
Identifiers
NPS Report Number
Sponsors
Funder
Format
88 p.;28 cm.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.