Feasibility analysis and design of a fault tolerant computing system: a TMR microprocessor system design of 64-Bit COTS microprocessors
Eken, Huseyin Baha
Ross, Alan A.
Loomis, Herschel H.
MetadataShow full item record
The purpose of this thesis is to analyze and determine the feasibility of implementing a fault tolerant computing system that is able to function in the presence of radiation induced Single Event Upsets (SEU) by using the Triple Modular Redundancy (TMR) technique with 64-bit Commercial-Off-The- Shelf (COTS) microprocessors. Due to the radiation environment in space, electronic devices must be designed to tolerate the radiation effects. While there are radiation-hardened devices that can tolerate radiation effects, they offer lower performance and higher cost than COTS devices. On the other hand, COTS devices offer lower cost, orders of magnitude higher performance, shorter design time and better software availability and compatibility. However, COTS devices are susceptible to the radiation effects. In order to use COTS devices in space environment, a fault tolerance technique such as TMR needs to be implemented. This thesis presents the design and analysis of a TMR 64-bit COTS microprocessor implementation. The system incorporates three 64-bit microprocessors, the memory system including SRAM and PROM memory modules and the programmable logic devices that are used to implement the IMR technique. The validity of the design is verified by the timing analysis conducted on read and write operations.
RightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
Showing items related by title, author, creator and subject.
Completion and testing of a TMR computing testbed and recommendations for a flight-ready follow-on design. Hofheinz, Damen O. (Monterey, California. Naval Postgraduate School, 2000);This thesis focuses on the completion and hardware testing of a fault tolerant computer system utilizing Triple Modular Redundancy (TMR). Due to the radiation environment in space, electronics in space applications must ...
Fault tolerant computing testbed: a tool for the analysis of hardware and software fault handling techniques Payne, John C. (Monterey, California. Naval Postgraduate School, 1998);Operating computers in space requires the use of very expensive radiation hardened microelectronics devices. Unfortunately, the United States radiation hardened market is rapidly shrinking and makes up a very small percentage ...
Implementation of a fault tolerant computing testbed: a tool for the analysis of hardware and software fault handling techniques Summers, David C. (Monterey, California. Naval Postgraduate School, 2000);With spacecraft designs placing more emphasis on reduced cost, faster design time, and higher performance, it is easy to understand why more commercial-off-the-shelf (COTS) devices are being used in space based applications. ...