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dc.contributor.advisorLoomis, Herschel H.
dc.contributor.authorJohnson, Steven A.
dc.date.accessioned2012-03-14T17:30:35Z
dc.date.available2012-03-14T17:30:35Z
dc.date.issued2003-03
dc.identifier.urihttp://hdl.handle.net/10945/1101
dc.description.abstractThe space environment has unique hazards that force electronic systems designers to use different techniques to build their systems. Radiation can cause Single Event Upsets (SEUs) which can cause state changes in satellite systems. Mitigation techniques have been developed to either prevent or recover from these upsets when they occur. At the same time, modifying on-orbit systems is difficult in a hardwired electronic system. Finding an alternative to either working around a mistake or having to keep the same generation of technology for years is important to the space community. Newer programmable logic devices such as Field Programmable Gate Arrays (FPGAs) allow for emulation of complex logic circuits, such as microprocessors. FPGAs can be repro-grammed as necessary, to account for errors in design, or upgrades in software logic circuits. In an effort to provide one solution for both of these issues, this research was undertaken. The Configurable Fault Tolerant Processor (CFTP) emulates three identical processors, using Triple Modular Redundancy (TMR) to mitigate SEUs on a radiation tolerant FPGA. With the reconfigurable capabilities of FPGA technology, as newer processors can be emulated, these new configurations can be uploaded to the satellite as software code, thereby actually upgrading the processor in flight. This research used a 16-bit Reduced Instruction Set Computer (RISC) processor as its cores. This thesis describes how the Harvard architecture of the processor is interfaced with the Von Neumann architecture of the memory. It also develops the process by which errors are detected and corrected, as well as recorded. The end result is a design simulation ready for implementation on an FPGA.en_US
dc.description.urihttp://archive.org/details/implementationof109451101
dc.format.extentxviii, 119 p. : ill. (some col.) ;en_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.en_US
dc.subject.lcshField programmable gate arraysen_US
dc.titleImplementation of a configurable fault tolerant processor (CFTP)en_US
dc.typeThesisen_US
dc.contributor.secondreaderRoss, Alan A.
dc.contributor.departmentElectrical Engineering
dc.description.serviceLieutenant, United States Navyen_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
etd.verifiednoen_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.


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