An investigation of the symmetric properties of logical functions
dc.contributor.advisor | Turner, John B. | |
dc.contributor.advisor | Cotton, Mitchell L. | |
dc.contributor.author | Barr, Robert M. | |
dc.date.accessioned | 2012-08-29T23:32:46Z | |
dc.date.available | 2012-08-29T23:32:46Z | |
dc.date.issued | 1960 | |
dc.identifier.uri | http://hdl.handle.net/10945/12475 | |
dc.description.abstract | The desired response of a logical network can be expressed as a one column matrix of bistable elements, defining the "function" of the network. To date methods of logical network synthesis and simplification have been concerned with manipulations of the network input?. This investigation treats with the network design as a manipulation of symmetrical properties of the fiinction itself. It will be shown that this treatment not onn y leads to a logical expression for the network configuration, but can also provide a clue to desirable properties cf circuit elements not yet designed, as developed, the network representation will take the form cf conventional and- or gating plus a postulated complementing device. | en_US |
dc.description.uri | http://archive.org/details/aninvestigationo1094512475 | |
dc.language.iso | en_US | |
dc.publisher | Monterey, California: U.S. Naval Postgraduate School | en_US |
dc.subject.lcsh | Electronics | en_US |
dc.title | An investigation of the symmetric properties of logical functions | en_US |
dc.type | Thesis | en_US |
dc.contributor.department | Electronics | |
dc.description.service | Lieutenant Commander, United States Navy | en_US |
etd.thesisdegree.name | M.S. in Engineering Electronics | en_US |
etd.thesisdegree.level | Masters | en_US |
etd.thesisdegree.discipline | Engineering Electronics | en_US |
etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
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