Naval Postgraduate School
Theses and Dissertations
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The minimization of multiple valued logic expressions using parallel processors
(Monterey, California. Naval Postgraduate School, 1991-09)
The process of finding an exact minimization for a multiple-valued logic (MVL) expression requires an extensive search and enormous computation time. One of the heuristics to reduce this computation time is the Neighborhood ...
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Lieutenant Junior Grade, Turkish Navy (1)
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1991 (1)
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Electrical Engineering (1)
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Electronic Warfare Academic Group (1)
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