Symmetrical residue-to-binary conversion algorithm, pipelined FPGA implementation, and testing logic for use in high-speed folding digitizers
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Authors
Monta, Ross Alan
Subjects
Advisors
Pace, Phillip E.
Fouts, Douglas
Date of Issue
2005-12
Date
Publisher
Monterey, CA; Naval Postgraduate School
Language
Abstract
The robust symmetrical number system (RSNS) can play a significant role in the reduction of encoding errors within a low-power folding analog-to-digital converter (ADC). A key part of this ADC design is the logic block that converts the symmetrical residues from each channel into a more convenient binary output. This thesis describes a robust symmetrical residue-to-binary conversion algorithm for moduli 1 7 m =, 2 8 m = and 3 9 m = (ADC dynamic range M = 126). Also described is a pipelined digital logic implementation for use in high speed programmable logic or application specific integrated circuits. To verify correct outputs of the robust symmetrical residue-to-binary conversion algorithm, a digital test circuit is described that generates the thermometer code (symmetrical residues) for the 3-channel ADC design.
Type
Thesis
Description
Series/Report No
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
xvi, 67 p. : ill. (some col.) ;
Citation
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.