Design, implementation, and testing of a high performance summation adder for radar image synthesis
Amundson, Craig A.
MetadataShow full item record
This thesis documents the schematic design, simulation, and fabrication mask layout of a highspeed 16-bit summation adder to be integrated into the Digital Image Synthesizer (DIS) Application Specific Integrated Circuit (ASIC). The DIS is a single-chip false target radar image generator to be used in countering wide band imaging radars. The DIS will calculate the false target image in 512 range bins. Each range bit utilizes two identical 16-bit binary adders. The 16-Bit Adder must compute the sum of two 16-bit numbers, providing a 16-bit sum, carry output, and overflow detection bit. The stated goal is for this adder to perform all of these functions in one pipeline stage while being clocked at 600 MHz. The first part of the design process includes an extensive analysis to utilize the fewest gates in designing the simplest adder that can achieve the 600 MHz goal. SPICE net lists are extracted from these schematic designs and simulations conducted to verify logic functionality and propagation speed. Mask layout of the verified design is constructed using a CMOS 0.18 micron process utilizing deep submicron technology with six metal interconnect layers. The mask layout design is verified by ensuring all design rule checks (DRC) and layout versus schematic (LVS) checks are satisfied. In aAddition, conclusions and recommendations are provided to assist other DIS project members in using this adder and the aforementioned design process for additional components of the DIS ASIC.
RightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
Showing items related by title, author, creator and subject.
Automatic layout techniques for the graphical editor in the Computer Aided Prototyping System (CAPS) Ray, William J (Monterey, California. Naval Postgraduate School, 1997-09);The Computer Aided Prototyping System (CAPS) is a systems engineering tool intended to make the iterative process of software development more efficient. The simplest way to input and modify a CAPS design is through the ...
Lee, Hoon S. (Monterey, California. Naval Postgraduate School, 1988-12);The contribution of this thesis is the development of a CAD (computer aided design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is only the second known MVL CAD tool and the first CAD tool for MVL ...
Human factors engineering and operability in the design of Electronic Warfare spaces aboard United States Naval combatants Blauser, David J. Jr. (Piscataway, N.J. : IEEE Press ; Hoboken, N.J. : Wiley, 1985-09);The purpose of this thesis is to present and discuss a method of assessing the effectiveness of a work space layout. In addition, this method will provide the framework for pinpointing those areas of layout design where ...