Design, implementation, and evaluation of a virtual shared memory system in a multi-transputer network.

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designimplementa00hart.pdf (4.96 MB)
Authors
Hart, Simon J.
Subjects
OCCAM
transputer
multi-transputer network
delay insertion loop
virtual shared memory
Advisors
Kodres, Uno R.
Date of Issue
1987-12
Date
December 1987
Publisher
Language
en_US
Abstract
This thesis presents the design, implementation, and evaluation of a virtual shared memory in a multi-Transputer network. The thesis explores the Transputer hardware implementation model and highlights the important details that programmers of such systems may need before being able to optimize such networks. All the programs and examples presented in this thesis were implemented in the OCCAM programming language, using the Transputer Development System, D700C, Beta 2.0 March 1987 compiler version.
Type
Thesis
Description
URI
https://hdl.handle.net/10945/22733
Series/Report No
Department
Computer Science
Organization
Naval Postgraduate School (U.S.)
Identifiers
NPS Report Number
Sponsors
Funder
Format
106 p.
Citation
Distribution Statement
Approved for public release; distribution is unlimited.
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Copyright is reserved by the copyright owner
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