Naval Postgraduate School
Dudley Knox Library
NPS Dudley Knox Library
View Item 
  •   Calhoun Home
  • Theses and Dissertations
  • 1. Thesis and Dissertation Collection, all items
  • View Item
  •   Calhoun Home
  • Theses and Dissertations
  • 1. Thesis and Dissertation Collection, all items
  • View Item
  • How to search in Calhoun
  • My Accounts
  • Ask a Librarian
JavaScript is disabled for your browser. Some features of this site may not work without it.

Browse

All of CalhounCollectionsThis Collection

My Account

LoginRegister

Statistics

Most Popular ItemsStatistics by CountryMost Popular Authors

A CAD tool for current-mode multiple-valued CMOS circuits

Thumbnail
Download
Iconcadtoolforcurren00leeh.pdf (4.924Mb)
Download Record
Download to EndNote/RefMan (RIS)
Download to BibTex
Author
Lee, Hoon S.
Date
1988-12
Advisor
Butler, Jon T.
Yurchak, J.M.
Second Reader
Yang, Chyan
Metadata
Show full item record
Abstract
The contribution of this thesis is the development of a CAD (computer aided design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is only the second known MVL CAD tool and the first CAD tool for MVL CMOS. The tool accepts a specification of the function to be realized by the user, produces a minimal or near-minimal realization (if such a realization is possible), and produces a layout of a programmable logic array (PLA) integrated circuit that realizes the given function. The layout is in MAGIC format, suitable for submission to a chip manufacturer. The CAD tool also allows the user to simulate the realized function so that he/she can verify correctness of design. The CAD tool is designed also to be an analysis tool for heuristic minimization algorithms. As part of this thesis, a random function generator and statistics gathering package were developed. In the present tool, two heuristics are provided and the user can choose one or both. In the latter case, the better realization is output to the user. The CAD tool is designed to be flexible, so that future improvements can be made in the heuristic algorithms, as well as the layout generator. Thus, the tool can be used to accommodate new technologies, for example, a voltage mode CMOS PLA rather than the current mode CMOS currently implemented.
Rights
Copyright is reserved by the copyright owner
URI
http://hdl.handle.net/10945/22935
Collections
  • 1. Thesis and Dissertation Collection, all items

Related items

Showing items related by title, author, creator and subject.

  • Thumbnail

    The use of searching algorithms for the minimization of Multi-Valued Logic functions 

    Watts, Alan W. (Monterey, California: Naval Postgraduate School, 1990-06);
    The goal of this thesis was to develop a searching algorithm for simplifying Multi-Valued Logic (MVL) functions. The algorithm was implemented as a program written in C for the UNIZ operating system. The algorithm accepts ...
  • Thumbnail

    On the equivalence of cost functions in the design of circuits by cost-tables 

    Schueller, Kriss A.; Butler, Jon T. (1990-06);
    n the costtable approach to logic design, a function is realized as a combination of functions from a table. The objective of the synthesis is to find the least cost realization, where realization cost is the sum of ...
  • Thumbnail

    The design of a predictive read cache 

    Robert, Joseph R., Jr. (Monterey, California. Naval Postgraduate School, 1996-03);
    The objective of this research has been the creation of a hardware design for a Predictive Read Cache (PRC). The PRC is a developmental cache intended to replace second-level caches common in modern microprocessor systems. ...
NPS Dudley Knox LibraryDUDLEY KNOX LIBRARY
Feedback

411 Dyer Rd. Bldg. 339
Monterey, CA 93943
circdesk@nps.edu
(831) 656-2947
DSN 756-2947

    Federal Depository Library      


Start Your Research

Research Guides
Academic Writing
Ask a Librarian
Copyright at NPS
Graduate Writing Center
How to Cite
Library Liaisons
Research Tools
Thesis Processing Office

Find & Download

Databases List
Articles, Books & More
NPS Theses
NPS Faculty Publications: Calhoun
Journal Titles
Course Reserves

Use the Library

My Accounts
Request Article or Book
Borrow, Renew, Return
Tech Help
Remote Access
Workshops & Tours

For Faculty & Researchers
For International Students
For Alumni

Print, Copy, Scan, Fax
Rooms & Study Spaces
Floor Map
Computers & Software
Adapters, Lockers & More

Collections

NPS Archive: Calhoun
Restricted Resources
Special Collections & Archives
Federal Depository
Homeland Security Digital Library

About

Hours
Library Staff
About Us
Special Exhibits
Policies
Our Affiliates
Visit Us

NPS-Licensed Resources—Terms & Conditions
Copyright Notice

Naval Postgraduate School

Naval Postgraduate School
1 University Circle, Monterey, CA 93943
Driving Directions | Campus Map

This is an official U.S. Navy Website |  Please read our Privacy Policy Notice  |  FOIA |  Section 508 |  No FEAR Act |  Whistleblower Protection |  Copyright and Accessibility |  Contact Webmaster

Export search results

The export option will allow you to export the current search results of the entered query to a file. Different formats are available for download. To export the items, click on the button corresponding with the preferred download format.

A logged-in user can export up to 15000 items. If you're not logged in, you can export no more than 500 items.

To select a subset of the search results, click "Selective Export" button and make a selection of the items you want to export. The amount of items that can be exported at once is similarly restricted as the full export.

After making a selection, click one of the export format buttons. The amount of items that will be exported is indicated in the bubble next to export format.